Computational architecture to address the challenge of large data volume in search engines.

Executing big data applications such as search engines is energy expensive and requires high throughput data processing. Part of the inefficiency data comes from accessing data between local storage and memory and cloud storage. Additionally, the ratio of processing units to memory storage is fixed by the computer architecture and is, therefore, not customizable for big data applications.

The system reconfigures the architecture of memory and storage in a computer to offload functions away from the central and intelligence processing units (CPU and IPU). This allows direct access to both local and remote memory, with high bandwidth and low latency. This reduces both software and hardware efficiency limitations and allows for application-dependent CPU/Memory ratios application.

A set of logically disaggregated interconnections supports indices that cannot fit into local storage and memory (CPU and IPU). The network consists of Peripheral Component Interconnect Express (PCIe) switches, allowing the field-programmable gate array to access both local and remote memory. Similarly, the memory network serves local and remote requests, however, it uses a point-to-point connection instead of the switch-based network to reduce latency.

• Fifteen microsecond latency for data access, 100x lower than CPU-based systems
• 160 GB/s bandwidth, 8x higher than conventional CPU servers
• Enables adaptation to accommodate different index algorithm schemes and different index sizes