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High-Performance Graphene Hall Sensors With Scalable Complementary Metal-Oxide Semiconductor (CMOS) Integration

Methods to harness the full potential of graphene Hall sensors through integration with CMOS integrated circuits for improved performance while mitigating undesirable effects.

Problem:

Two-dimensional materials (2DM), such as graphene, hold enormous potential in electronic devices due to their exceptional performance and new functionalities. Graphene Hall-effect magnetic field sensors (GHSs) offer higher sensitivity and faster response to magnetic fields compared to commercial silicon magnetic-field sensors, making them a promising option for improving the performance of sensor arrays in applications such as magnetic imaging and biosensing. However, the 2D nature of these materials introduces challenges such as performance heterogeneity, offset, and noise, limiting their practical appeal and commercial adoption compared to silicon devices with poorer performance but higher reliability. Current efforts to address these issues focus on improving material synthesis, a process that is both costly and difficult to scale.

Solution:

The inventors have developed methods to address concerns regarding the variability and scalability of GHSs. They have introduced a new device architecture for independent tuning of each GHS to reduce the effects of sensor variability without compromising performance. Additionally, they have implemented physical fabrication techniques and circuit strategies designed with built-in resilience to the inherent performance heterogeneity of 2DMs.

Technology:

To address the response heterogeneity in GHSs, the lab has designed a GHS device architecture that allows for the independent tuning of individual sensors on a single substrate, circuit strategies implemented in silicon-integrated circuit technology, and fabrication techniques to integrate GHSs with the silicon-integrated circuit.

The design features an insulated backgate terminal located beneath the central region of the Hall cross which modulates the carrier density within the active region of the GHS. This individual tuning approach reduces the high variability inherent to GHSs without sacrificing performance.

Furthermore, the custom CMOS-integrated circuit includes a per-sensor digital calibration mechanism that independently controls the gate voltage of each GHS, correcting for sensitivity, non-uniformity, and drifting across devices. Additionally, the readout architecture employs a spinning-current architecture that reduces GHS offset and low-frequency noise.

Finally, to monolithically integrate GHSs into the back-end layers of a CMOS process, the GHSs are embedded within the inter-layer dielectric underneath the top metal layer, allowing direct connection to the CMOS circuitry with high GHS yield.

Advantages:

Individual tuning reduces variability in GHS arrays from >30% to <2% with minimal impact on the array sensitivity
The backgate contact voltage can be changed dynamically to operate the same sensor in different device regimes
The CMOS-integrated GHSs demonstrated comparable magnetic sensing performance to GHSs fabricated on a conventional silicon substrate
CMOS integration enables high GHS array density (32 sensing sites and tuning/readout circuitry within <2 mm² chip area)

Fig. 1: (Left) Schematic of a conventional GHS implementation on an oxide-coated silicon substrate. The local non-idealities lead to variations in performance between devices. (Right) Schematic of the designed GHS tuning mechanism, in which each device is fabricated with a local insulated backgate terminal, relaxing the tradeoff between uniformity and performance. Fig. 2: CMOS-graphene Hall sensor integration concept and processing steps. (A) Concept diagram of the Hall sensors integrated within the back-end-of-line layers of the CMOS chip and vertically connected to silicon front-end-of-line electronics. (B) Cross-sectional diagram of the CMOS chip during various steps of the GHS integration process.